Noise optimization of an inductively degenerated CMOS low noise amplifier

Research output: Contribution to journalArticlepeer-review


This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels
Original languageEnglish
Pages (from-to)835-841
JournalIEEE Transactions on Circuits and Systems - 2, Analog and Digital Signal Processing
Issue number9
Publication statusPublished - 2001

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering


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