Optimal System-on-Chip Test Scheduling

Erik Larsson; Hideo Fujiwara

doi:10.1109/ATS.2003.1250828

Optimal System-on-Chip Test Scheduling

Erik Larsson, Hideo Fujiwara

External Organization - Unknown

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

Original language	English
Title of host publication	[Host publication title missing]
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	306-311
ISBN (Print)	0-7695-1951-2
DOIs	https://doi.org/10.1109/ATS.2003.1250828
Publication status	Published - 2003
Externally published	Yes
Event	12th IEEE Asian Test Symposium ATS03 - Xi'an, China Duration: 2003 Nov 16 → 2003 Nov 19

Publication series

Name
ISSN (Print)	1081-7735

Conference

Conference	12th IEEE Asian Test Symposium ATS03
Country/Territory	China
City	Xi'an
Period	2003/11/16 → 2003/11/19

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

test scheduling
test access mechanisms
TAM
test conflicts
test wrappers
TAM routing

Access to Document

10.1109/ATS.2003.1250828

Cite this

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title = "Optimal System-on-Chip Test Scheduling",

abstract = "In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.",

keywords = "test scheduling, test access mechanisms, TAM, test conflicts, test wrappers, TAM routing",

author = "Erik Larsson and Hideo Fujiwara",

year = "2003",

doi = "10.1109/ATS.2003.1250828",

language = "English",

isbn = "0-7695-1951-2",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

pages = "306--311",

booktitle = "[Host publication title missing]",

address = "United States",

note = "12th IEEE Asian Test Symposium ATS03 ; Conference date: 16-11-2003 Through 19-11-2003",

}

TY - GEN

T1 - Optimal System-on-Chip Test Scheduling

AU - Larsson, Erik

AU - Fujiwara, Hideo

PY - 2003

Y1 - 2003

N2 - In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

AB - In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

KW - test scheduling

KW - test access mechanisms

KW - TAM

KW - test conflicts

KW - test wrappers

KW - TAM routing

UR - https://www.scopus.com/pages/publications/34648833691

U2 - 10.1109/ATS.2003.1250828

DO - 10.1109/ATS.2003.1250828

M3 - Paper in conference proceeding

SN - 0-7695-1951-2

SP - 306

EP - 311

BT - [Host publication title missing]

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th IEEE Asian Test Symposium ATS03

Y2 - 16 November 2003 through 19 November 2003

ER -

Optimal System-on-Chip Test Scheduling

Abstract

Publication series

Conference

Subject classification (UKÄ)

Free keywords

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Cite this