Performance improvement for H.264 video encoding using ILP embedded processor

Ali Iranpour; Krzysztof Kuchcinski

doi:10.1109/DSD.2006.77

Performance improvement for H.264 video encoding using ILP embedded processor

Ali Iranpour, Krzysztof Kuchcinski

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

In this paper, we examine the impact of instruction level parallelism (ILP) on the full H.264 video encoding application and give quantitative performance measures of a superscalar architecture. Most research efforts have concentrated on the data intensive parts, such as kernels but these are taking less time from the entire execution as encoders are using new, more efficient algorithms. This important fact cannot be neglected since new video encoding standards have been proposed and the amount of other than data intensive computations has increased significantly. We observed significant improvement for the entire application when using superscalar architecture with out-of-order execution scheme. Tradeoffs in superscalar performance are also evaluated with combinations of measurements from simplescalar simulator

Original language	English
Title of host publication	9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	515-521
Number of pages	7
ISBN (Print)	0-7695-2609-8
DOIs	https://doi.org/10.1109/DSD.2006.77
Publication status	Published - 2006
Event	9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools - Dubrovnik, Croatia Duration: 2006 Aug 30 → 2006 Sept 1

Conference

Conference	9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools
Country/Territory	Croatia
City	Dubrovnik
Period	2006/08/30 → 2006/09/01

Subject classification (UKÄ)

Computer Sciences

Free keywords

data intensive computations
superscalar architecture
instruction level parallelism embedded processor
performance improvement
H.264 video encoding standards
out-of-order execution scheme
simplescalar simulator

Access to Document

10.1109/DSD.2006.77

Cite this

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title = "Performance improvement for H.264 video encoding using ILP embedded processor",

abstract = "In this paper, we examine the impact of instruction level parallelism (ILP) on the full H.264 video encoding application and give quantitative performance measures of a superscalar architecture. Most research efforts have concentrated on the data intensive parts, such as kernels but these are taking less time from the entire execution as encoders are using new, more efficient algorithms. This important fact cannot be neglected since new video encoding standards have been proposed and the amount of other than data intensive computations has increased significantly. We observed significant improvement for the entire application when using superscalar architecture with out-of-order execution scheme. Tradeoffs in superscalar performance are also evaluated with combinations of measurements from simplescalar simulator",

keywords = "data intensive computations, superscalar architecture, instruction level parallelism embedded processor, performance improvement, H.264 video encoding standards, out-of-order execution scheme, simplescalar simulator",

author = "Ali Iranpour and Krzysztof Kuchcinski",

year = "2006",

doi = "10.1109/DSD.2006.77",

language = "English",

isbn = "0-7695-2609-8",

pages = "515--521",

booktitle = "9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools ; Conference date: 30-08-2006 Through 01-09-2006",

}

Iranpour, A & Kuchcinski, K 2006, Performance improvement for H.264 video encoding using ILP embedded processor. in 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 515-521, 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Dubrovnik, Croatia, 2006/08/30. https://doi.org/10.1109/DSD.2006.77

Performance improvement for H.264 video encoding using ILP embedded processor. / Iranpour, Ali; Kuchcinski, Krzysztof.
9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools. IEEE - Institute of Electrical and Electronics Engineers Inc., 2006. p. 515-521.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

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AU - Iranpour, Ali

AU - Kuchcinski, Krzysztof

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N2 - In this paper, we examine the impact of instruction level parallelism (ILP) on the full H.264 video encoding application and give quantitative performance measures of a superscalar architecture. Most research efforts have concentrated on the data intensive parts, such as kernels but these are taking less time from the entire execution as encoders are using new, more efficient algorithms. This important fact cannot be neglected since new video encoding standards have been proposed and the amount of other than data intensive computations has increased significantly. We observed significant improvement for the entire application when using superscalar architecture with out-of-order execution scheme. Tradeoffs in superscalar performance are also evaluated with combinations of measurements from simplescalar simulator

AB - In this paper, we examine the impact of instruction level parallelism (ILP) on the full H.264 video encoding application and give quantitative performance measures of a superscalar architecture. Most research efforts have concentrated on the data intensive parts, such as kernels but these are taking less time from the entire execution as encoders are using new, more efficient algorithms. This important fact cannot be neglected since new video encoding standards have been proposed and the amount of other than data intensive computations has increased significantly. We observed significant improvement for the entire application when using superscalar architecture with out-of-order execution scheme. Tradeoffs in superscalar performance are also evaluated with combinations of measurements from simplescalar simulator

KW - data intensive computations

KW - superscalar architecture

KW - instruction level parallelism embedded processor

KW - performance improvement

KW - H.264 video encoding standards

KW - out-of-order execution scheme

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BT - 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools

Y2 - 30 August 2006 through 1 September 2006

ER -

Performance improvement for H.264 video encoding using ILP embedded processor

Abstract

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Subject classification (UKÄ)

Free keywords

Access to Document

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Cite this