Abstract
This paper describes power optimization techniques applied to a reconfigurable digital finite impulse response (FIR) filter used in a Universal Mobile Telephone Service (UMTS) mobile terminal. Various methods of optimization for implementation were combined to achieve low cost in terms of power consumption. Each optimization method is described in detail and is applied to the reconfigurable filter. The optimization methods have achieved a 78.8% reduction in complexity for the multipliers in the FIR structure. A comparison of synthesized RTL models of the original and the optimized architectures resulted in a 27% reduction in look-up tables when targeted for the Xilinx Virtex II Pro field programmable gate array (FPGA). An automated method for transformation of coefficient multipliers into bit-shifts is also presented
| Original language | English |
|---|---|
| Title of host publication | 2004 IEEE Workshop on Signal Processing Systems Design and Implementation |
| Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
| Pages | 321-324 |
| ISBN (Print) | 0-7803-8504-7 |
| DOIs | |
| Publication status | Published - 2004 |
| Event | 2004 IEEE Workshop on Signal Processing Systems Design and Implementation - Austin, TX, United States Duration: 2004 Oct 13 → 2004 Oct 15 |
Conference
| Conference | 2004 IEEE Workshop on Signal Processing Systems Design and Implementation |
|---|---|
| Country/Territory | United States |
| City | Austin, TX |
| Period | 2004/10/13 → 2004/10/15 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- field programmable gate array
- Xilinx Virtex II Pro
- look-up tables
- synthesized RTL models
- power consumption
- UMTS mobile terminal
- Universal Mobile Telephone Service
- digital finite impulse response filter
- power optimization
- reconfigurable FIR-filter
- FPGA
- coefficient multipliers
- bit-shifts
- automated method