Record performance for junctionless transistors in InGaAs MOSFETs

Cezar B. Zota; Mattias Borg; Lars Erik Wernersson; Erik Lind

doi:10.23919/VLSIT.2017.7998190

Record performance for junctionless transistors in InGaAs MOSFETs

Cezar B. Zota, Mattias Borg, Lars Erik Wernersson, Erik Lind

Nano Electronics

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

We demonstrate junctionless tri-gate MOSFETs utilizing a single layer 7 nm thick In_0.80Ga_0.20As (N_D ∼ 1×10¹⁹ cm^-3) as both channel and contacts. Devices with source and drain metal separation of 32 nm and L_g of 25 nm exhibit SS = 76 mV/dec., both the highest reported g_m = 1.6 mS/μα and I_on = 160 μA/μm (V_DD = 0.5 V, I_OFF = 100 nA/μm) for a junctionless transistor. We also examine the influence of the contact thickness, comparing double-layer junctionless devices with 37 nm thick contacts with single-layer 7 nm contact devices.

Original language	English
Title of host publication	2017 Symposium on VLSI Technology, VLSI Technology 2017
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	T34-T35
ISBN (Electronic)	9784863486058
DOIs	https://doi.org/10.23919/VLSIT.2017.7998190
Publication status	Published - 2017 Jul 31
Event	37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, Japan Duration: 2017 Jun 5 → 2017 Jun 8

Conference

Conference	37th Symposium on VLSI Technology, VLSI Technology 2017
Country/Territory	Japan
City	Kyoto
Period	2017/06/05 → 2017/06/08

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.23919/VLSIT.2017.7998190

Cite this

@inproceedings{1f7d58f273f044b2b7bde69991745788,

title = "Record performance for junctionless transistors in InGaAs MOSFETs",

abstract = "We demonstrate junctionless tri-gate MOSFETs utilizing a single layer 7 nm thick In0.80Ga0.20As (ND ∼ 1×1019 cm-3) as both channel and contacts. Devices with source and drain metal separation of 32 nm and Lg of 25 nm exhibit SS = 76 mV/dec., both the highest reported gm = 1.6 mS/μα and Ion = 160 μA/μm (VDD = 0.5 V, IOFF = 100 nA/μm) for a junctionless transistor. We also examine the influence of the contact thickness, comparing double-layer junctionless devices with 37 nm thick contacts with single-layer 7 nm contact devices.",

author = "Zota, {Cezar B.} and Mattias Borg and Wernersson, {Lars Erik} and Erik Lind",

year = "2017",

month = jul,

day = "31",

doi = "10.23919/VLSIT.2017.7998190",

language = "English",

pages = "T34--T35",

booktitle = "2017 Symposium on VLSI Technology, VLSI Technology 2017",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "37th Symposium on VLSI Technology, VLSI Technology 2017 ; Conference date: 05-06-2017 Through 08-06-2017",

}

Zota, CB, Borg, M , Wernersson, LE & Lind, E 2017, Record performance for junctionless transistors in InGaAs MOSFETs. in 2017 Symposium on VLSI Technology, VLSI Technology 2017., 7998190, IEEE - Institute of Electrical and Electronics Engineers Inc., pp. T34-T35, 37th Symposium on VLSI Technology, VLSI Technology 2017, Kyoto, Japan, 2017/06/05. https://doi.org/10.23919/VLSIT.2017.7998190

Record performance for junctionless transistors in InGaAs MOSFETs. / Zota, Cezar B.; Borg, Mattias ; Wernersson, Lars Erik et al.
2017 Symposium on VLSI Technology, VLSI Technology 2017. IEEE - Institute of Electrical and Electronics Engineers Inc., 2017. p. T34-T35 7998190.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Record performance for junctionless transistors in InGaAs MOSFETs

AU - Zota, Cezar B.

AU - Borg, Mattias

AU - Wernersson, Lars Erik

AU - Lind, Erik

PY - 2017/7/31

Y1 - 2017/7/31

N2 - We demonstrate junctionless tri-gate MOSFETs utilizing a single layer 7 nm thick In0.80Ga0.20As (ND ∼ 1×1019 cm-3) as both channel and contacts. Devices with source and drain metal separation of 32 nm and Lg of 25 nm exhibit SS = 76 mV/dec., both the highest reported gm = 1.6 mS/μα and Ion = 160 μA/μm (VDD = 0.5 V, IOFF = 100 nA/μm) for a junctionless transistor. We also examine the influence of the contact thickness, comparing double-layer junctionless devices with 37 nm thick contacts with single-layer 7 nm contact devices.

AB - We demonstrate junctionless tri-gate MOSFETs utilizing a single layer 7 nm thick In0.80Ga0.20As (ND ∼ 1×1019 cm-3) as both channel and contacts. Devices with source and drain metal separation of 32 nm and Lg of 25 nm exhibit SS = 76 mV/dec., both the highest reported gm = 1.6 mS/μα and Ion = 160 μA/μm (VDD = 0.5 V, IOFF = 100 nA/μm) for a junctionless transistor. We also examine the influence of the contact thickness, comparing double-layer junctionless devices with 37 nm thick contacts with single-layer 7 nm contact devices.

U2 - 10.23919/VLSIT.2017.7998190

DO - 10.23919/VLSIT.2017.7998190

M3 - Paper in conference proceeding

AN - SCOPUS:85028066295

SP - T34-T35

BT - 2017 Symposium on VLSI Technology, VLSI Technology 2017

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 37th Symposium on VLSI Technology, VLSI Technology 2017

Y2 - 5 June 2017 through 8 June 2017

ER -

Record performance for junctionless transistors in InGaAs MOSFETs

Abstract

Conference

Subject classification (UKÄ)

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