Abstract
Most of the power consumption has in the past been related to the dynamic activities, in a CMOS circuit. However, the static power, i.e. leakage, is a major contribution to the total power consumption, in present nano-meter scale technologies. This paper discusses static power reduction methodologies on architectural and arithmetical level. Novel arithmetic techniques to reduce the static power consumption in digital applications for nano-scale CMOS technologies are addressed. An arithmetic reduction of the static power consumption down to 5 % by using bit-serial arithmetic compared to bit-parallel is indicated.
Original language | English |
---|---|
Pages | 306-309 |
Publication status | Published - 2007 |
Event | IEEE 14th International Conference on Electronics, Circuits and Systems (ICECS 2007) - Marrakech, Morocco Duration: 2007 Dec 11 → 2007 Dec 14 |
Conference
Conference | IEEE 14th International Conference on Electronics, Circuits and Systems (ICECS 2007) |
---|---|
Country/Territory | Morocco |
City | Marrakech |
Period | 2007/12/11 → 2007/12/14 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering