Reducing On-chip Memory for Massive MIMO Baseband Processing using Channel Compression

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review


Employing a large number of antennas at the base station, massive MIMO significantly improves spectral efficiency and transmit power efficiency. On the other hand, massive MIMO also introduces unprecedented implementation challenges, especially in terms of processing and storage of large-size channel state information (CSI) matrices. Since on-chip memory is generally very expensive and has limited storage capacity, this paper uses the concept of on-chip CSI data compression and decompression to reduce memory requirements during baseband processing. To achieve this, massive MIMO channel properties are explored using a hardware-friendly DFT-based compression algorithm. The proposed method is evaluated with measured channel data at 2.6 GHz using a 128-antenna linear array [1]. Simulation results show that aggressive CSI compression can be adopted without significant loss in communication performance, while the DFT-based compression can be conveniently integrated into the on-chip memory. This enables a large reduction of required on-chip memory, with negligible hardware overhead for compression/decompression.
Original languageEnglish
Title of host publication2017 IEEE 86th Vehicular Technology Conference: VTC2017-Fall
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages5
Publication statusPublished - 2018
Event2017 IEEE 86th Vehicular Technology Conference (VTC-Fall) - Hilton Toronto, Toronto, Canada
Duration: 2017 Sept 242017 Sept 27


Conference2017 IEEE 86th Vehicular Technology Conference (VTC-Fall)

Subject classification (UKÄ)

  • Other Electrical Engineering, Electronic Engineering, Information Engineering


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