Abstract
It is common to embed instruments when developing integrated circuits (ICs). These instruments are accessed at post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and operator-driven in-field test. At any of these scenarios, it is of interest to access some but not all of the instruments. IEEE 1149.1-2013 and IEEE 1687 propose Test Access Port based (TAP-based) mechanisms to design flexible scan networks such that any combination of instruments can be accessed from outside of the IC. Previous works optimize TAP-based scan networks for one scenario with a known number of accesses. However, at design time, it is difficult to foresee all needed scenarios and the exact number of accesses to instruments. Moreover, the number of accesses might change due to late design changes, addition/exclusion of tests, and changes of constraints. In this paper, we analyze and compare seven IEEE 1687 compatible network design approaches in terms of instrument access time, hardware overhead, and robustness. Given the similarities between IEEE 1149.1-2013 and IEEE 1687, the conclusions are also applicable to IEEE 1149.1-2013 networks.
Original language | English |
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Title of host publication | [Host publication title missing] |
Number of pages | 10 |
DOIs | |
Publication status | Published - 2014 |
Event | IEEE International Test Conference, 2014 - Seattle, United States Duration: 2014 Oct 21 → 2014 Oct 23 |
Conference
Conference | IEEE International Test Conference, 2014 |
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Country/Territory | United States |
City | Seattle |
Period | 2014/10/21 → 2014/10/23 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering