Second Harmonic 60-GHz Power Amplifiers in 130-nm CMOS

Johan Wernehag, Henrik Sjöland

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

150 Downloads (Pure)

Abstract

Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. The 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.
Original languageEnglish
Title of host publicationProceeding of IEEE Ph. D. Research in Microelectronics and Electronics
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages149-152
Number of pages4
Publication statusPublished - 2007
EventIEEE Ph. D. Research in Microelectronics and Electronics - Bordeaux
Duration: 2007 Jul 22007 Jul 5

Conference

ConferenceIEEE Ph. D. Research in Microelectronics and Electronics
Period2007/07/022007/07/05

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Fingerprint

Dive into the research topics of 'Second Harmonic 60-GHz Power Amplifiers in 130-nm CMOS'. Together they form a unique fingerprint.

Cite this