Semiconductor nanowires as a novel electronic materials technology for future electronic devices

Abstract in Undetermined
Extreme down-scaling of nanoelectronic devices by top-down fabrication methods may be hindered by several obstacles, such as the cost for patterning and processing, or inferior device performance due to process-induced damage. In this presentation I will present a bottom-up approach for nanometer-scale device fabrication, based on seeded growth of semiconductor nanowires, using a method traditionally described as vapor-liquid-solid (VLS) growth. I will try to summarize how this approach has, in just 3-4 years, moved the technology from quite poorly controlled sprouting of nanowires without real control of dimensions or location, to a much more mature technology by which positioning and dimensions of nanowires as monolithic extensions of the substrate wafer are tightly controlled, and with the ability to create atomically abrupt and complex heterostructure devices, enabling devices such as resonant-tunneling diodes and single-electron transistors to be created. I will also show, as maybe the greatest promise for the impact of the technology, that our nanowire technology may make it possible to incorporate advantages of ni-V heterostructure device technology onto silicon substrates. Finally, I will present recent progress in the technology for implementation of planar processing technology for wrap-gate nanowire field-effect transistors, yielding high-quality room temperature transistor performance. Acknowledgements: This work is based on the contributions from many colleagues and Ph.D.-students, as reported in papers listed below. The work is performed within the Nanometer Structure Consortium at Lund University (http://nano.lth.se) and is supported by grants from the Swedish Foundation for Strategic Research (SSF), the Swedish Research Council (VR), the US Office of Naval Research (ONR), and the Knut and Alice Wallenberg Foundation (KAW).