Sizing of Dual-V-T Gates for Sub-V-T Circuits

Babak Mohammadi; Syed Muhammad Yasser Sherazi; Joachim Rodrigues

doi:10.1109/SubVT.2012.6404305

Sizing of Dual-V-T Gates for Sub-V-T Circuits

Babak Mohammadi, Syed Muhammad Yasser Sherazi, Joachim Rodrigues

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.

Original language	English
Title of host publication	2012 IEEE Subthreshold Microelectronics Conference (SubVT)
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	978-1-4673-1586-9
DOIs	https://doi.org/10.1109/SubVT.2012.6404305
Publication status	Published - 2012
Event	IEEE Subthreshold Microelectronics Conference (SubVT) - Waltham, MA Duration: 2012 Oct 9 → 2012 Oct 10

Conference

Conference	IEEE Subthreshold Microelectronics Conference (SubVT)
Period	2012/10/09 → 2012/10/10

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Access to Document

10.1109/SubVT.2012.6404305

Cite this

@inproceedings{022a53f3889848178e8eed3a1133612d,

title = "Sizing of Dual-V-T Gates for Sub-V-T Circuits",

abstract = "This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.",

author = "Babak Mohammadi and Sherazi, {Syed Muhammad Yasser} and Joachim Rodrigues",

year = "2012",

doi = "10.1109/SubVT.2012.6404305",

language = "English",

isbn = "978-1-4673-1586-9",

booktitle = "2012 IEEE Subthreshold Microelectronics Conference (SubVT)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE Subthreshold Microelectronics Conference (SubVT) ; Conference date: 09-10-2012 Through 10-10-2012",

}

TY - GEN

T1 - Sizing of Dual-V-T Gates for Sub-V-T Circuits

AU - Mohammadi, Babak

AU - Sherazi, Syed Muhammad Yasser

AU - Rodrigues, Joachim

PY - 2012

Y1 - 2012

N2 - This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.

AB - This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.

U2 - 10.1109/SubVT.2012.6404305

DO - 10.1109/SubVT.2012.6404305

M3 - Paper in conference proceeding

SN - 978-1-4673-1586-9

BT - 2012 IEEE Subthreshold Microelectronics Conference (SubVT)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Subthreshold Microelectronics Conference (SubVT)

Y2 - 9 October 2012 through 10 October 2012

ER -

Sizing of Dual-V-T Gates for Sub-V-T Circuits

Abstract

Conference

Subject classification (UKÄ)

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