Abstract
We have successfully embedded a metal gate in-between two resonant tunneling double barrier heterostructures (RTD), thus realizing a three dimensional resonant tunneling transistor. The gate is placed 30 nm above and 100 below the two RTD's, respectively. The asymmetric gate allows for a unique control of the current-voltage characteristics, not only controlling the peak current but also the peak voltage. We have modeled the transistor with Cadence, a standard simulation package for circuit simulations, achieving good agreement with experimental data
| Original language | English |
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| Title of host publication | 7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science |
| Publisher | Lund University |
| Number of pages | 2 |
| Publication status | Published - 2002 |
| Event | Proceedings of 7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science (NANO-7/ECOSS-21) - Malmö, Sweden Duration: 2002 Jun 24 → 2002 Jun 28 |
Conference
| Conference | Proceedings of 7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science (NANO-7/ECOSS-21) |
|---|---|
| Country/Territory | Sweden |
| City | Malmö |
| Period | 2002/06/24 → 2002/06/28 |
Subject classification (UKÄ)
- Condensed Matter Physics (including Material Physics, Nano Physics)
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- circuit simulations
- peak voltage
- simulation package
- stacking
- peak current
- heterostructures
- metallic elements
- submicron resonant tunneling transistor
- metal gate
- resonant tunneling double barrier heterostructures
- three dimensional resonant tunneling transistor
- current-voltage characteristics
- asymmetric gate
- 30 to 100 nm
- W-GaAs