Supply-Voltage Down Conversion for Digital CMOS Designs

Peter Nilsson, Mohammed Azher Ali, Manivannan Ethiraj, Syed Muhammad Yasser Sherazi

Research output: Contribution to conferencePaper, not in proceedingpeer-review

Abstract

This paper presents a methodology to reduce the power consumption, by using multiple supply voltage levels. The voltage levels are scaled down from a single supply voltage, by the use of a diode-connected device. Only one single device is used per conversion, which gives a small area overhead. No inductors and no off-chip components are used. The methodology is tested on different constellations of inverters and on anti-aliasing filters. A power reduction down to 47% in the filters with reduced supply voltage and down to 72% in the complete filter is shown.
Original languageEnglish
Number of pages4
Publication statusPublished - 2014
EventIEEE 21th International Conference on Electronics, Circuits and Systems, 2014 - Marseille, France
Duration: 2014 Dec 72014 Dec 10

Conference

ConferenceIEEE 21th International Conference on Electronics, Circuits and Systems, 2014
Abbreviated titleICECS 2014
Country/TerritoryFrance
CityMarseille
Period2014/12/072014/12/10

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

  • Application specific integrated circuits
  • digital circuits
  • CMOS integrated circuits
  • digital filters
  • low-pass filters
  • low-power electronics
  • and DC-DC converters.

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