Teaching digital HW-design by implementing a complete MP3 decoder

Hugo Hedberg; Thomas Lenart; Henrik Svensson; Peter Nilsson; Viktor Öwall

doi:10.1109/MSE.2003.1205241

Teaching digital HW-design by implementing a complete MP3 decoder

Hugo Hedberg, Thomas Lenart, Henrik Svensson, Peter Nilsson, Viktor Öwall

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work hard towards a common goal

Original language	English
Title of host publication	[Host publication title missing]
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	31-32
ISBN (Print)	0-7695-1973-3
DOIs	https://doi.org/10.1109/MSE.2003.1205241
Publication status	Published - 2003
Event	IEEE International Conference on Microelectronic Systems Education (MSE), 2003 - Anaheim, CA, United States Duration: 2003 Jun 1 → 2003 Jun 2

Conference

Conference	IEEE International Conference on Microelectronic Systems Education (MSE), 2003
Country/Territory	United States
City	Anaheim, CA
Period	2003/06/01 → 2003/06/02

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

VHSIC HDL
VHDL
very high speed integrated circuits
hardware description languages
educational courses
MP3 decoder
netlist generation
integrated circuit verification
integrated circuit fabrication
application specific integrated circuits
integrated circuits architecture selection
digital HW-design
teaching
project course
hardware design
ASIC design

Access to Document

10.1109/MSE.2003.1205241

Cite this

@inproceedings{81db5170cdba4470b5aa87f20ff34df0,

title = "Teaching digital HW-design by implementing a complete MP3 decoder",

abstract = "This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work hard towards a common goal",

keywords = "VHSIC HDL, VHDL, very high speed integrated circuits, hardware description languages, educational courses, MP3 decoder, netlist generation, integrated circuit verification, integrated circuit fabrication, application specific integrated circuits, integrated circuits architecture selection, digital HW-design, teaching, project course, hardware design, ASIC design",

author = "Hugo Hedberg and Thomas Lenart and Henrik Svensson and Peter Nilsson and Viktor {\"O}wall",

year = "2003",

doi = "10.1109/MSE.2003.1205241",

language = "English",

isbn = "0-7695-1973-3",

pages = "31--32",

booktitle = "[Host publication title missing]",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International Conference on Microelectronic Systems Education (MSE), 2003 ; Conference date: 01-06-2003 Through 02-06-2003",

}

Hedberg, H, Lenart, T, Svensson, H, Nilsson, P & Öwall, V 2003, Teaching digital HW-design by implementing a complete MP3 decoder. in [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 31-32, IEEE International Conference on Microelectronic Systems Education (MSE), 2003, Anaheim, CA, United States, 2003/06/01. https://doi.org/10.1109/MSE.2003.1205241

TY - GEN

T1 - Teaching digital HW-design by implementing a complete MP3 decoder

AU - Hedberg, Hugo

AU - Lenart, Thomas

AU - Svensson, Henrik

AU - Nilsson, Peter

AU - Öwall, Viktor

PY - 2003

Y1 - 2003

N2 - This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work hard towards a common goal

AB - This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work hard towards a common goal

KW - VHSIC HDL

KW - VHDL

KW - very high speed integrated circuits

KW - hardware description languages

KW - educational courses

KW - MP3 decoder

KW - netlist generation

KW - integrated circuit verification

KW - integrated circuit fabrication

KW - application specific integrated circuits

KW - integrated circuits architecture selection

KW - digital HW-design

KW - teaching

KW - project course

KW - hardware design

KW - ASIC design

U2 - 10.1109/MSE.2003.1205241

DO - 10.1109/MSE.2003.1205241

M3 - Paper in conference proceeding

SN - 0-7695-1973-3

SP - 31

EP - 32

BT - [Host publication title missing]

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Microelectronic Systems Education (MSE), 2003

Y2 - 1 June 2003 through 2 June 2003

ER -

Teaching digital HW-design by implementing a complete MP3 decoder

Abstract

Conference

Subject classification (UKÄ)

Free keywords

Access to Document

Fingerprint

Cite this