Test Cost Reduction of 3D Stacked ICs: Test Planning and Test Flow Selection

Breeta Sengupta

Research output: ThesisDoctoral Thesis (monograph)

345 Downloads (Pure)


Ever higher levels of integration within the Integrated Circuit (IC) to
meet progressively widening scope of its application in respect of functionality,
size, performance and manufacturing issues inspired development
of the three-dimensional (3D) Stacked IC as a device having
viable architecture. However, with increased complexity, manufacturing
cost increased. The manufacturing cost includes the test cost component,
essential to ensure fidelity to the desired design specifications.
Of the several challenges faced by 3D Stacked ICs, cost efficient testing
of the manufactured product is most critical. Reduction of test cost for
3D Stacked ICs through test planning along with test flow selection
methods is addressed in this thesis.
Test planning for 3D Stacked ICs is performed by reducing the total
cost accounting for the test time and Design-for-Test (DfT) hardware.
Three test architecture standards are used: Built-In Self-Test (BIST),
IEEE 1149.1 and IEEE 1500. The test cost corresponding to each test
architecture is detailed and test planning algorithms are proposed. The
algorithms are implemented and experiments are performed on several
3D Stacked IC designs formed with multiple 2D IC benchmarks. For
experiment, a test flow is presented that comprises the wafer test of
each chip followed by test of the entire packaged IC. Results indicate
effectiveness of the proposed algorithms in terms of test cost.
Test flow selection, to decide stages at which tests are to be performed,
for 3D Stacked ICs is addressed motivated towards the reduction
of test time required to produce each single fault-free package. A
model to calculate the total test time for any given test flow is detailed.
An algorithm is proposed to find a test flow for reducing test time.
The algorithm is implemented and executed on several 3D Stacked IC
designs with up to ten chips in the stack. Results indicate considerable
reductions in test time as compared to predetermined test flows.
Original languageEnglish
Awarding Institution
  • Department of Electrical and Information Technology
  • Larsson, Erik, Supervisor
  • Öwall, Viktor, Supervisor
Award date2020 Sept 4
ISBN (Print)978-91-7895-562-6
ISBN (electronic) 978-91-7895-563-3
Publication statusPublished - 2020 Jun 11

Bibliographical note

Defence details
Date: 2020-09-04
Time: 9:00
Place: Lecture hall E:1408, building E, John Ericssons väg 2, Faculty of Engineering LTH, Lund University, Lund. Join via Zoom: https://lu-se.zoom.us/j/66036051217
External reviewer(s)
Name: Singh, Adit
Title: Prof.
Affiliation: Aburn University, USA.

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Computer Science

Free keywords

  • 3D Stacked Integrated Circuits (3D SIC), Test Cost, Optimization, Test Flow, Design for Test (DfT), Test Application Time (TAT)


Dive into the research topics of 'Test Cost Reduction of 3D Stacked ICs: Test Planning and Test Flow Selection'. Together they form a unique fingerprint.

Cite this