Test Planning and Test Access Mechanism Design for Stacked Chips using ILP

Breeta Sengupta, Erik Larsson

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

5 Citations (SciVal)
114 Downloads (Pure)

Abstract

In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC’02 benchmarks. The experimental results
show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips.
Original languageEnglish
Title of host publicationVLSI Test Symposium (VTS), 2014 IEEE 32nd
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages1-6
Number of pages6
DOIs
Publication statusPublished - 2014
EventIEEE VLSI Test Symposium (VTS) - Napa, CA, United States
Duration: 2014 Apr 132014 Apr 17

Publication series

Name
ISSN (Print)1093-0167

Conference

ConferenceIEEE VLSI Test Symposium (VTS)
Country/TerritoryUnited States
CityNapa, CA
Period2014/04/132014/04/17

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • DfT (Design for test)
  • Test Architecture
  • Scan chain
  • Wrapper Chain
  • Test Scheduling
  • Test Time.
  • 3D Stacked Integrated Circuit (SIC)
  • Integer Linear Programming (ILP)

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