Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Breeta Sengupta; Urban Ingelsson; Erik Larsson

doi:10.1109/VLSID.2012.111

Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Breeta Sengupta, Urban Ingelsson, Erik Larsson

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

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Abstract

Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

Original language	English
Title of host publication	[Host publication title missing]
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	442-447
Number of pages	6
DOIs	https://doi.org/10.1109/VLSID.2012.111
Publication status	Published - 2012
Event	2012 25th International Conference on VLSI Design - Hyderbad, India Duration: 2012 Jan 7 → …

Conference

Conference	2012 25th International Conference on VLSI Design
Country/Territory	India
City	Hyderbad
Period	2012/01/07 → …

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering

Free keywords

Test Scheduling
3D stacked IC
JTAG
Test Architecture
Through Silicon Via

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10.1109/VLSID.2012.111

brese_VLSI12

Cite this

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title = "Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias",

abstract = "Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.",

keywords = "Test Scheduling, 3D stacked IC, JTAG, Test Architecture, Through Silicon Via",

author = "Breeta Sengupta and Urban Ingelsson and Erik Larsson",

year = "2012",

doi = "10.1109/VLSID.2012.111",

language = "English",

pages = "442--447",

booktitle = "[Host publication title missing]",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2012 25th International Conference on VLSI Design ; Conference date: 07-01-2012",

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AU - Sengupta, Breeta

AU - Ingelsson, Urban

AU - Larsson, Erik

PY - 2012

Y1 - 2012

N2 - Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

AB - Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.

KW - Test Scheduling

KW - 3D stacked IC

KW - JTAG

KW - Test Architecture

KW - Through Silicon Via

U2 - 10.1109/VLSID.2012.111

DO - 10.1109/VLSID.2012.111

M3 - Paper in conference proceeding

SP - 442

EP - 447

BT - [Host publication title missing]

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 2012 25th International Conference on VLSI Design

Y2 - 7 January 2012

ER -

Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Abstract

Conference

Subject classification (UKÄ)

Free keywords

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Cite this