Test Time Analysis for IEEE P1687

Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review


The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.
Original languageEnglish
Title of host publicationTest Symposium (ATS), 2010 19th IEEE Asian
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)978-1-4244-8841-4
Publication statusPublished - 2010
Externally publishedYes
Event19th IEEE Asian Test Symposium (ATS10) - Shanghai, China
Duration: 2010 Dec 12010 Dec 4


Conference19th IEEE Asian Test Symposium (ATS10)

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering


Dive into the research topics of 'Test Time Analysis for IEEE P1687'. Together they form a unique fingerprint.

Cite this