Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes

Mojtaba Mahdavi; Liang Liu; Ove Edfors; Michael Lentmaier; Norbert Wehn; Stefan  Weithoffer

doi:10.1109/ISTC49272.2021.9594185

Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes

Mojtaba Mahdavi, Liang Liu, Ove Edfors, Michael Lentmaier, Norbert Wehn, Stefan Weithoffer

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

Having close-to-capacity performance and low error floor, even for small block lengths, make spatially coupled serially concatenated codes (SC-SCCs) a very promising class of codes. However, classical window decoding of SC-SCCs either limits the minimum block length or requires a large number of iterations, which increases the complexity and constrains the degree to which an SC-SCC decoder architecture can be parallelized. In this paper we propose jumping window decoding (JWD), an algorithmic modification to the scheduling of decoding such that it enables pipelined implementation of SC-SCCs decoder. Also, it provides flexibility in terms of block length and number of iterations and makes them independent of each other. Simulation results show that our scheme outperforms classical window decoding of both SC-SCCs and uncoupled SCCs, in terms of performance. Furthermore, we present a fully pipelined hardware architecture to realize JWD of SC-SCCs along with area estimates in 12nm technology for the respective case study.

Original language	English
Title of host publication	IEEE International Symposium on Topics in Coding (ISTC), 2021
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	1-5
Number of pages	5
ISBN (Electronic)	978-1-6654-0943-8
ISBN (Print)	978-1-6654-0944-5
DOIs	https://doi.org/10.1109/ISTC49272.2021.9594185
Publication status	Published - 2021 Jun 30
Event	IEEE International Symposium on Topics in Coding (ISTC), 2021 - Montreal, Canada Duration: 2021 Aug 30 → 2021 Sept 3 https://istc2021.org/index.html

Conference

Conference	IEEE International Symposium on Topics in Coding (ISTC), 2021
Country/Territory	Canada
City	Montreal
Period	2021/08/30 → 2021/09/03
Internet address	https://istc2021.org/index.html

Subject classification (UKÄ)

Communication Systems
Other Electrical Engineering, Electronic Engineering, Information Engineering
Signal Processing

Free keywords

channel coding
turbo-like codes
Spatially coupled codes
VLSI Implementation
window decoding
pipeline decoding
serially concatenated convolutional codes (SCCCs)
hardware architecture
decoding thresholds
decoding latency
decoding performance
Hardware Implementation
coupling memory
convolutional encoder
Throughput

Access to Document

10.1109/ISTC49272.2021.9594185

1 Doctoral Thesis (compilation)

Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design
Mahdavi, M., 2021 Mar 20, Dpt. of Electrical and Information Technology, Lund University, Sweden. 253 p.
Research output: Thesis › Doctoral Thesis (compilation)

Open Access
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Cite this

@inproceedings{a135b204f63e4e06a407a0f65c9c76c2,

title = "Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes",

abstract = "Having close-to-capacity performance and low error floor, even for small block lengths, make spatially coupled serially concatenated codes (SC-SCCs) a very promising class of codes. However, classical window decoding of SC-SCCs either limits the minimum block length or requires a large number of iterations, which increases the complexity and constrains the degree to which an SC-SCC decoder architecture can be parallelized. In this paper we propose jumping window decoding (JWD), an algorithmic modification to the scheduling of decoding such that it enables pipelined implementation of SC-SCCs decoder. Also, it provides flexibility in terms of block length and number of iterations and makes them independent of each other. Simulation results show that our scheme outperforms classical window decoding of both SC-SCCs and uncoupled SCCs, in terms of performance. Furthermore, we present a fully pipelined hardware architecture to realize JWD of SC-SCCs along with area estimates in 12nm technology for the respective case study.",

keywords = "channel coding, turbo-like codes, Spatially coupled codes, VLSI Implementation, window decoding, pipeline decoding, serially concatenated convolutional codes (SCCCs), hardware architecture, decoding thresholds, decoding latency, decoding performance, Hardware Implementation, coupling memory, convolutional encoder, Throughput",

author = "Mojtaba Mahdavi and Liang Liu and Ove Edfors and Michael Lentmaier and Norbert Wehn and Stefan Weithoffer",

year = "2021",

month = jun,

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doi = "10.1109/ISTC49272.2021.9594185",

language = "English",

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booktitle = "IEEE International Symposium on Topics in Coding (ISTC), 2021",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International Symposium on Topics in Coding (ISTC), 2021 ; Conference date: 30-08-2021 Through 03-09-2021",

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}

Mahdavi, M, Liu, L , Edfors, O , Lentmaier, M, Wehn, N & Weithoffer, S 2021, Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes. in IEEE International Symposium on Topics in Coding (ISTC), 2021. IEEE - Institute of Electrical and Electronics Engineers Inc., pp. 1-5, IEEE International Symposium on Topics in Coding (ISTC), 2021, Montreal, Canada, 2021/08/30. https://doi.org/10.1109/ISTC49272.2021.9594185

Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes. / Mahdavi, Mojtaba; Liu, Liang ; Edfors, Ove et al.
IEEE International Symposium on Topics in Coding (ISTC), 2021. IEEE - Institute of Electrical and Electronics Engineers Inc., 2021. p. 1-5.

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

TY - GEN

T1 - Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes

AU - Mahdavi, Mojtaba

AU - Liu, Liang

AU - Edfors, Ove

AU - Lentmaier, Michael

AU - Wehn, Norbert

AU - Weithoffer, Stefan

PY - 2021/6/30

Y1 - 2021/6/30

N2 - Having close-to-capacity performance and low error floor, even for small block lengths, make spatially coupled serially concatenated codes (SC-SCCs) a very promising class of codes. However, classical window decoding of SC-SCCs either limits the minimum block length or requires a large number of iterations, which increases the complexity and constrains the degree to which an SC-SCC decoder architecture can be parallelized. In this paper we propose jumping window decoding (JWD), an algorithmic modification to the scheduling of decoding such that it enables pipelined implementation of SC-SCCs decoder. Also, it provides flexibility in terms of block length and number of iterations and makes them independent of each other. Simulation results show that our scheme outperforms classical window decoding of both SC-SCCs and uncoupled SCCs, in terms of performance. Furthermore, we present a fully pipelined hardware architecture to realize JWD of SC-SCCs along with area estimates in 12nm technology for the respective case study.

AB - Having close-to-capacity performance and low error floor, even for small block lengths, make spatially coupled serially concatenated codes (SC-SCCs) a very promising class of codes. However, classical window decoding of SC-SCCs either limits the minimum block length or requires a large number of iterations, which increases the complexity and constrains the degree to which an SC-SCC decoder architecture can be parallelized. In this paper we propose jumping window decoding (JWD), an algorithmic modification to the scheduling of decoding such that it enables pipelined implementation of SC-SCCs decoder. Also, it provides flexibility in terms of block length and number of iterations and makes them independent of each other. Simulation results show that our scheme outperforms classical window decoding of both SC-SCCs and uncoupled SCCs, in terms of performance. Furthermore, we present a fully pipelined hardware architecture to realize JWD of SC-SCCs along with area estimates in 12nm technology for the respective case study.

KW - channel coding

KW - turbo-like codes

KW - Spatially coupled codes

KW - VLSI Implementation

KW - window decoding

KW - pipeline decoding

KW - serially concatenated convolutional codes (SCCCs)

KW - hardware architecture

KW - decoding thresholds

KW - decoding latency

KW - decoding performance

KW - Hardware Implementation

KW - coupling memory

KW - convolutional encoder

KW - Throughput

U2 - 10.1109/ISTC49272.2021.9594185

DO - 10.1109/ISTC49272.2021.9594185

M3 - Paper in conference proceeding

SN - 978-1-6654-0944-5

SP - 1

EP - 5

BT - IEEE International Symposium on Topics in Coding (ISTC), 2021

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Topics in Coding (ISTC), 2021

Y2 - 30 August 2021 through 3 September 2021

ER -

Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes

Abstract

Conference

Subject classification (UKÄ)

Free keywords

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Research output

Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design

Cite this