Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si: Processing in 3D

Lars Erik Wernersson

doi:10.1109/DRC.2016.7548411

Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si: Processing in 3D

Lars Erik Wernersson

Department of Electrical and Information Technology

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

III-V MOSFETs are candidates for extension of the scaling roadmap beyond 10 nm. In the vertical direction, the requirements on gate-length scaling is less stringent and vertical III-V nanowire FETs are thus attractive for high density and low-power applications. While growth in the vertical direction allows flexibility in heterostructure combination and eases the path for integration on Si substrates, the processing in the vertical direction is still regarded challenging. Processing on the length scale of a few tens of nanometers has nevertheless been demonstrated including processing of vertical nanowire transistors with a diameter of 10 nm. Besides logic applications, III-V MOSFETs hold promises in the area of millimeter-wave electronics.

Original language	English
Title of host publication	74th Annual Device Research Conference, DRC 2016
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Volume	2016-August
ISBN (Electronic)	9781509028276
DOIs	https://doi.org/10.1109/DRC.2016.7548411
Publication status	Published - 2016 Aug 22
Event	74th Annual Device Research Conference, DRC 2016 - Newark, United States Duration: 2016 Jun 19 → 2016 Jun 22

Conference

Conference	74th Annual Device Research Conference, DRC 2016
Country/Territory	United States
City	Newark
Period	2016/06/19 → 2016/06/22

Subject classification (UKÄ)

Nano-technology

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10.1109/DRC.2016.7548411

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title = "Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si: Processing in 3D",

abstract = "III-V MOSFETs are candidates for extension of the scaling roadmap beyond 10 nm. In the vertical direction, the requirements on gate-length scaling is less stringent and vertical III-V nanowire FETs are thus attractive for high density and low-power applications. While growth in the vertical direction allows flexibility in heterostructure combination and eases the path for integration on Si substrates, the processing in the vertical direction is still regarded challenging. Processing on the length scale of a few tens of nanometers has nevertheless been demonstrated including processing of vertical nanowire transistors with a diameter of 10 nm. Besides logic applications, III-V MOSFETs hold promises in the area of millimeter-wave electronics.",

author = "Wernersson, {Lars Erik}",

year = "2016",

month = aug,

day = "22",

doi = "10.1109/DRC.2016.7548411",

language = "English",

volume = "2016-August",

booktitle = "74th Annual Device Research Conference, DRC 2016",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "74th Annual Device Research Conference, DRC 2016 ; Conference date: 19-06-2016 Through 22-06-2016",

}

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T1 - Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si

T2 - 74th Annual Device Research Conference, DRC 2016

AU - Wernersson, Lars Erik

PY - 2016/8/22

Y1 - 2016/8/22

N2 - III-V MOSFETs are candidates for extension of the scaling roadmap beyond 10 nm. In the vertical direction, the requirements on gate-length scaling is less stringent and vertical III-V nanowire FETs are thus attractive for high density and low-power applications. While growth in the vertical direction allows flexibility in heterostructure combination and eases the path for integration on Si substrates, the processing in the vertical direction is still regarded challenging. Processing on the length scale of a few tens of nanometers has nevertheless been demonstrated including processing of vertical nanowire transistors with a diameter of 10 nm. Besides logic applications, III-V MOSFETs hold promises in the area of millimeter-wave electronics.

AB - III-V MOSFETs are candidates for extension of the scaling roadmap beyond 10 nm. In the vertical direction, the requirements on gate-length scaling is less stringent and vertical III-V nanowire FETs are thus attractive for high density and low-power applications. While growth in the vertical direction allows flexibility in heterostructure combination and eases the path for integration on Si substrates, the processing in the vertical direction is still regarded challenging. Processing on the length scale of a few tens of nanometers has nevertheless been demonstrated including processing of vertical nanowire transistors with a diameter of 10 nm. Besides logic applications, III-V MOSFETs hold promises in the area of millimeter-wave electronics.

UR - http://www.scopus.com/inward/record.url?scp=84987754738&partnerID=8YFLogxK

U2 - 10.1109/DRC.2016.7548411

DO - 10.1109/DRC.2016.7548411

M3 - Paper in conference proceeding

AN - SCOPUS:84987754738

VL - 2016-August

BT - 74th Annual Device Research Conference, DRC 2016

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

Y2 - 19 June 2016 through 22 June 2016

ER -

Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si: Processing in 3D

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