Vertical III-V Nanowire MOSFETs

Olli-Pekka Kilpi

Research output: Thesis › Doctoral Thesis (compilation)

3 Paper in conference proceeding
2 Article
1 Letter

6 results

2019
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
Kilpi, O. P., Svensson, J., Lind, E. & Wernersson, L. E., 2019, In: IEEE Journal of the Electron Devices Society. 7, p. 70-75
Research output: Contribution to journal › Article › peer-review

Open Access
2018
Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si
Kilpi, O. P., Svensson, J. & Wernersson, L. E., 2018 Jan 23, 2017 IEEE International Electron Devices Meeting, IEDM 2017. IEEE - Institute of Electrical and Electronics Engineers Inc., Vol. Part F134366. p. 17.3.1-17.3.4
Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

File
296 Downloads (Pure)
2017
Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si
Kilpi, O. P., Svensson, J., Wu, J., Persson, A. R., Wallenberg, R., Lind, E. & Wernersson, L. E., 2017 Oct 11, In: Nano Letters. 17, 10, p. 6006-6010 5 p.
Research output: Contribution to journal › Article › peer-review

File
196 Downloads (Pure)
Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with I_on = 330 μa/μm at I_off = 100 nA/μm and V_D = 0.5 v
Kilpi, O. P., Wu, J., Svensson, J., Lind, E. & Wernersson, L. E., 2017 Jul 31, 2017 Symposium on VLSI Technology, VLSI Technology 2017. IEEE - Institute of Electrical and Electronics Engineers Inc., p. T36-T37 7998191
Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

File
111 Downloads (Pure)
2016
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
Berg, M., Kilpi, O.-P., Persson, K.-M., Svensson, J., Hellenbrand, M., Lind, E. & Wernersson, L.-E., 2016 Aug 8, In: IEEE Electron Device Letters. 37, 8, p. 966 - 969 4 p.
Research output: Contribution to journal › Letter › peer-review

Open Access
File
387 Downloads (Pure)
Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
Berg, M., Persson, K.-M., Kilpi, O.-P., Svensson, J., Lind, E. & Wernersson, L.-E., 2016 Feb 16, Technical Digest - International Electron Devices Meeting, IEDM. IEEE - Institute of Electrical and Electronics Engineers Inc., Vol. 2016-February. 7409806
Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

File
248 Downloads (Pure)

Vertical III-V Nanowire MOSFETs

Research output

Search results

Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si

Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si

Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with Ion = 330 μa/μm at Ioff = 100 nA/μm and VD = 0.5 v

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with I_on = 330 μa/μm at I_off = 100 nA/μm and V_D = 0.5 v