Vertical III-V Nanowire MOSFETs

Olli-Pekka Kilpi

Research output: Thesis › Doctoral Thesis (compilation)

3 Paper in conference proceeding
2 Article
1 Letter

3 results

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2018
Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si
Kilpi, O. P., Svensson, J. & Wernersson, L. E., 2018 Jan 23, 2017 IEEE International Electron Devices Meeting, IEDM 2017. IEEE - Institute of Electrical and Electronics Engineers Inc., Vol. Part F134366. p. 17.3.1-17.3.4
Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

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296 Downloads (Pure)
2017
Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with I_on = 330 μa/μm at I_off = 100 nA/μm and V_D = 0.5 v
Kilpi, O. P., Wu, J., Svensson, J., Lind, E. & Wernersson, L. E., 2017 Jul 31, 2017 Symposium on VLSI Technology, VLSI Technology 2017. IEEE - Institute of Electrical and Electronics Engineers Inc., p. T36-T37 7998191
Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

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111 Downloads (Pure)
2016
Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
Berg, M., Persson, K.-M., Kilpi, O.-P., Svensson, J., Lind, E. & Wernersson, L.-E., 2016 Feb 16, Technical Digest - International Electron Devices Meeting, IEDM. IEEE - Institute of Electrical and Electronics Engineers Inc., Vol. 2016-February. 7409806
Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

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248 Downloads (Pure)