Vertical III-V Nanowire Transistors for Low-Power Electronics

Research output: ThesisDoctoral Thesis (compilation)

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Abstract

Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission.
This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations.
Systematic fine tuning of the band alignment of the tunnel junction resulted
in achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/dec
and ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V.
Original languageEnglish
QualificationDoctor
Awarding Institution
  • Department of Electrical and Information Technology
Supervisors/Advisors
  • Wernersson, Lars-Erik, Supervisor
  • Svensson, Johannes, Assistant supervisor
Award date2023 May 26
Place of PublicationLund
Publisher
ISBN (Print)978-91-8039-706-3
ISBN (electronic) 978-91-8039-707-0
Publication statusPublished - 2023 Apr

Bibliographical note

Defence details
Date: 2023-05-26
Time: 09:15
Place: Lecture Hall E:1406, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund. The dissertation will be live streamed, but part of the premises is to be excluded from the live stream.
External reviewer(s)
Name: Gnani, Elena
Title: Associate Prof.
Affiliation: University of Bologna, Italy.
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Subject classification (UKÄ)

  • Nano Technology

Free keywords

  • metal-oxide-semiconductor field-effect transistor (MOSFET)
  • Steep slope
  • Tunnel Field-Effect Transistors
  • Vertical nanowire
  • III-V materials
  • semiconducting III-V
  • InAs
  • GaSb
  • InGaAsSb
  • PMOS
  • Transistor
  • Electronics

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