Vertical III-V Nanowire Tunnel Field-Effect Transistor

In this thesis fabrication and optimization of vertical III-V Tunneling Field-Effect transistors was explored. Usage of vertical nanowires, allows for combination of materials with large lattice mismatch in the same nanowire structure. TFETs in this thesis were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material quality. Usage of these material systems allowed for fabrication of devices with staggered and broken band-gap alignment. To fully harvest the benefits from these structures, the fabrication process was optimized. This was performed by exploring different spacer and gate technologies, required for vertical devices. Furthermore, improvement of electrostatics was achieved by reduction of the channel diameter and high-κ interface. Further improvements of the performance were achieved by scaling of the device dimensions such as nanowire lengths, spacer thickness, and gate-length. Used fabrication techniques allowed us to fabricate devices with a channel diameter of 11 nm. By switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, which allowed us to fabricate devices with record performance, reaching a minimum subthreshold swing of 48 mV/decade and a record high I₆₀ of 0.31 μA/μm at a drive voltage of 0.3 V. Stability of the process allowed us to demonstrate data from a large number of TFETs with ability to operate below the thermal limit of 60 mV/decade. This allowed us to study correlations between important device parameter such as: I₆₀, on-current, subthreshold swing, and off-current. Using transmission electron microscopy, the heterojunction was characterized. Furthermore, TCAD modeling was performed to understand what limits the performance of these devices. Also, electrical measurement of the random telegraph noise allowed us to understand the impact the oxide defects have on highly scaled devices.