Abstract
We report on InAs enhancement-mode field-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-kappa gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the TnAs/Si conduction band offset.
Original language | English |
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Pages (from-to) | 3037-3041 |
Journal | IEEE Transactions on Electron Devices |
Volume | 55 |
Issue number | 11 |
DOIs | |
Publication status | Published - 2008 |
Subject classification (UKÄ)
- Condensed Matter Physics
- Electrical Engineering, Electronic Engineering, Information Engineering
Free keywords
- nanowires (NWs)
- Field-effect transistor (FET)
- InAs
- on Si
- III-V
- wrap gate