Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade

Elvedin Memisevic; Johannes Svensson; Erik Lind; Lars Erik Wernersson

doi:10.1109/LED.2018.2836862

Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade

Elvedin Memisevic, Johannes Svensson, Erik Lind, Lars Erik Wernersson

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Abstract

We present experimental data from vertical InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors with channel diameter scaled down to 10 nm and ability to reach a point subthreshold swing of 35 mV/decade at VDS = 0.05 V. Furthermore, the impact of drain, channel and source diameter scaling on the subthreshold swing and currents are studied. Impact of gate-overlap is more evident for devices with highly scaled source due to strong reduction of the current. Furthermore, small channel diameter makes these devices more susceptible to Random Telegraph Signal noise.

Original language	English
Pages (from-to)	1089-1091
Journal	IEEE Electron Device Letters
Volume	39
Issue number	7
Early online date	2018 May 14
DOIs	https://doi.org/10.1109/LED.2018.2836862
Publication status	Published - 2018 Jul

Subject classification (UKÄ)

Nano-technology

Free keywords

GaSb
Heterojunctions
III-V
InAs
InGaAsSb
Logic gates
Nanoscale devices
Resistance
RTS
steep-slope
TFET
TFETs
Vertical Nanowires

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10.1109/LED.2018.2836862

InAs_InGaAsSb_GaSb_TFETs_MemisevicAccepted author manuscript, 1.16 MB

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title = "Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade",

abstract = "We present experimental data from vertical InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors with channel diameter scaled down to 10 nm and ability to reach a point subthreshold swing of 35 mV/decade at VDS = 0.05 V. Furthermore, the impact of drain, channel and source diameter scaling on the subthreshold swing and currents are studied. Impact of gate-overlap is more evident for devices with highly scaled source due to strong reduction of the current. Furthermore, small channel diameter makes these devices more susceptible to Random Telegraph Signal noise.",

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author = "Elvedin Memisevic and Johannes Svensson and Erik Lind and Wernersson, {Lars Erik}",

year = "2018",

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T1 - Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade

AU - Memisevic, Elvedin

AU - Svensson, Johannes

AU - Lind, Erik

AU - Wernersson, Lars Erik

PY - 2018/7

Y1 - 2018/7

N2 - We present experimental data from vertical InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors with channel diameter scaled down to 10 nm and ability to reach a point subthreshold swing of 35 mV/decade at VDS = 0.05 V. Furthermore, the impact of drain, channel and source diameter scaling on the subthreshold swing and currents are studied. Impact of gate-overlap is more evident for devices with highly scaled source due to strong reduction of the current. Furthermore, small channel diameter makes these devices more susceptible to Random Telegraph Signal noise.

AB - We present experimental data from vertical InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors with channel diameter scaled down to 10 nm and ability to reach a point subthreshold swing of 35 mV/decade at VDS = 0.05 V. Furthermore, the impact of drain, channel and source diameter scaling on the subthreshold swing and currents are studied. Impact of gate-overlap is more evident for devices with highly scaled source due to strong reduction of the current. Furthermore, small channel diameter makes these devices more susceptible to Random Telegraph Signal noise.

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KW - Heterojunctions

KW - III-V

KW - InAs

KW - InGaAsSb

KW - Logic gates

KW - Nanoscale devices

KW - Resistance

KW - RTS

KW - steep-slope

KW - TFET

KW - TFETs

KW - Vertical Nanowires

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DO - 10.1109/LED.2018.2836862

M3 - Article

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SP - 1089

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

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ER -

Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade

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