Wordlength Optimization of a Pipelined FFT Processor

Stefan Johansson, Shousheng He, Peter Nilsson

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceedingpeer-review

Abstract

This paper describes the optimization of the word lengths in an 8 k-points pipelined FFT processor. The word lengths can be freely chosen since the FFT is implemented as a full custom ASIC. According to the specification, input and output word lengths are 12 bits but improved performance on be achieved by using a longer wordlength internally. Increased wordlength means increased size, both for memory and arithmetic operations. Since the FFT processor uses large memories, especially in the early stages, it is especially important to keep wordlength short in the beginning of the pipeline. Finding a good trade-off between precision and size is a difficult problem and it is not reasonable to solve analytically. Simulations using a C-model are therefore used to find an acceptable solution. The simulations show that a good solution is obtained by starting with 12 bits and gradually increasing the wordlength up to 16 bits. The final result is rounded back to 12 bits. This is a good trade-off between precision and complexity
Original languageEnglish
Title of host publication42nd Midwest Symposium on Circuits and Systems, 1999.
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages501-503
Volume1
ISBN (Print)0-7803-5491-5
DOIs
Publication statusPublished - 1999
Event1999 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’99) - Las Cruces, New Mexico, United States
Duration: 1999 Aug 81999 Aug 11

Publication series

Name
Volume1

Conference

Conference1999 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’99)
Country/TerritoryUnited States
CityLas Cruces, New Mexico
Period1999/08/081999/08/11

Subject classification (UKÄ)

  • Electrical Engineering, Electronic Engineering, Information Engineering

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