Wrap-gated InAs nanowire field-effect transistor

Lars-Erik Wernersson; Tomas Bryllert; Erik Lind; Lars Samuelson

doi:10.1109/IEDM.2005.1609324

Wrap-gated InAs nanowire field-effect transistor

Lars-Erik Wernersson, Tomas Bryllert, Erik Lind, Lars Samuelson

Research output: Chapter in Book/Report/Conference proceeding › Paper in conference proceeding › peer-review

Abstract

Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at Vds ≡ 0.15 V (for Vg ≡ 0 V) and low voltage operation Vth ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design

Original language	English
Title of host publication	International Electron Devices Meeting 2005
Publisher	IEEE - Institute of Electrical and Electronics Engineers Inc.
Pages	273-276
Number of pages	4
ISBN (Print)	0-7803-9268-X
DOIs	https://doi.org/10.1109/IEDM.2005.1609324
Publication status	Published - 2005
Event	International Electron Devices Meeting 2005 - Washington, DC, United States Duration: 2005 Dec 5 → 2005 Dec 7

Conference

Conference	International Electron Devices Meeting 2005
Country/Territory	United States
City	Washington, DC
Period	2005/12/05 → 2005/12/07

Subject classification (UKÄ)

Electrical Engineering, Electronic Engineering, Information Engineering
Condensed Matter Physics

Free keywords

optical lithography
lattice constants
0.15 V
InAs
heterostructures design
lateral strain relaxation
drain induced barrier lowering
gate coupling
semiconductor nanowires
wrap gated nanowire
field effect transistor

Access to Document

10.1109/IEDM.2005.1609324

Cite this

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title = "Wrap-gated InAs nanowire field-effect transistor",

abstract = "Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at Vds ≡ 0.15 V (for Vg ≡ 0 V) and low voltage operation Vth ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design",

keywords = "optical lithography, lattice constants, 0.15 V, InAs, heterostructures design, lateral strain relaxation, drain induced barrier lowering, gate coupling, semiconductor nanowires, wrap gated nanowire, field effect transistor",

author = "Lars-Erik Wernersson and Tomas Bryllert and Erik Lind and Lars Samuelson",

year = "2005",

doi = "10.1109/IEDM.2005.1609324",

language = "English",

isbn = "0-7803-9268-X",

pages = "273--276",

booktitle = "International Electron Devices Meeting 2005",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "International Electron Devices Meeting 2005 ; Conference date: 05-12-2005 Through 07-12-2005",

}

TY - GEN

T1 - Wrap-gated InAs nanowire field-effect transistor

AU - Wernersson, Lars-Erik

AU - Bryllert, Tomas

AU - Lind, Erik

AU - Samuelson, Lars

PY - 2005

Y1 - 2005

N2 - Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at Vds ≡ 0.15 V (for Vg ≡ 0 V) and low voltage operation Vth ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design

AB - Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at Vds ≡ 0.15 V (for Vg ≡ 0 V) and low voltage operation Vth ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design

KW - optical lithography

KW - lattice constants

KW - 0.15 V

KW - InAs

KW - heterostructures design

KW - lateral strain relaxation

KW - drain induced barrier lowering

KW - gate coupling

KW - semiconductor nanowires

KW - wrap gated nanowire

KW - field effect transistor

U2 - 10.1109/IEDM.2005.1609324

DO - 10.1109/IEDM.2005.1609324

M3 - Paper in conference proceeding

SN - 0-7803-9268-X

SP - 273

EP - 276

BT - International Electron Devices Meeting 2005

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - International Electron Devices Meeting 2005

Y2 - 5 December 2005 through 7 December 2005

ER -

Wrap-gated InAs nanowire field-effect transistor

Abstract

Conference

Subject classification (UKÄ)

Free keywords

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Cite this