Abstract
The electrical properties of ZrO2 and HfO2 gate dielectrics on n-InAs were evaluated. Particularly, an in situ surface treatment method including cyclic nitrogen plasma and trimethylaluminum pulses was used to improve the quality of the high-κ oxides. The quality of the InAs-oxide interface was evaluated with a full equivalent circuit model developed for narrow band gap metal-oxide-semiconductor (MOS) capacitors. Capacitance-voltage (C-V) measurements exhibit a total trap density profile with a minimum of 1 × 1012 cm-2 eV-1 and 4 × 1012 cm-2 eV-1 for ZrO2 and HfO2, respectively, both of which are comparable to the best values reported for high-κ/III-V devices. Our simulations showed that the measured capacitance is to a large extent affected by the border trap response suggesting a very low density of interface traps. Charge trapping in MOS structures was also investigated using the hysteresis in the C-V measurements. The experimental results demonstrated that the magnitude of the hysteresis increases with increase in accumulation voltage, indicating an increase in the charge trapping response.
Original language | English |
---|---|
Article number | 132904 |
Journal | Applied Physics Letters |
Volume | 108 |
Issue number | 13 |
DOIs | |
Publication status | Published - 2016 Mar 28 |
Subject classification (UKÄ)
- Electrical Engineering, Electronic Engineering, Information Engineering