Pietro Andreani

Senior Lecturer
More filtering options
  1. 2019
  2. A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

    Siyu Tan, Sundstrom, L., Palm, M., Sven Mattisson & Pietro Andreani, 2019 Nov 21, 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. Nurmi, J., Ellervee, P., Halonen, K. & Roning, J. (eds.). Institute of Electrical and Electronics Engineers Inc., 8906969

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  3. 2018
  4. 2017
  5. A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS

    Mahmoud, A., Pietro Andreani & Pepe, F., 2017 Nov, In : IEEE Microwave and Wireless Components Letters. 27, 11, p. 1010-1012

    Research output: Contribution to journalArticle

  6. On the Remarkable Performance of the Series-Resonance CMOS Oscillator

    Pepe, F., Bevilacqua, A. & Pietro Andreani, 2017 Aug 1, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 99, 12 p.

    Research output: Contribution to journalArticle

  7. A general theory of phase noise in transconductor-based harmonic oscillators

    Pepe, F. & Pietro Andreani, 2017 Feb 1, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, p. 432-445 14 p., 7723864.

    Research output: Contribution to journalArticle

  8. 2016
  9. A continuous-time delta-sigma ADC with integrated digital background calibration

    Siyu Tan, Miao, Y., Palm, M., Joachim Neves Rodrigues & Pietro Andreani, 2016 Nov 1, In : Analog Integrated Circuits and Signal Processing. 89, 2, p. 273-282 10 p.

    Research output: Contribution to journalArticle

  10. A 65 nm CMOS Wideband Radio Receiver with ΔΣ-Based A/D-Converting Channel-Select Filters

    Xiaodong Liu, Nejdel, A., Palm, M., Sundstrom, L., Markus Törmänen, Henrik Sjöland & Pietro Andreani, 2016 Jul 1, In : IEEE Journal of Solid-State Circuits. 51, 7, p. 1566-1578 13 p., 7469322.

    Research output: Contribution to journalArticle

  11. Still More on the 1/f2 Phase Noise Performance of Harmonic Oscillators

    Pepe, F. & Pietro Andreani, 2016 Jun 1, In : IEEE Transactions on Circuits and Systems - II - Express Briefs. 63, 6, p. 538-542 5 p., 7407326.

    Research output: Contribution to journalArticle

  12. A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process

    Mahmoud, A., Fanori, L., Mattsson, T., Caputa, P. & Piero Andreani, 2016 May 23, In : Analog Integrated Circuits and Signal Processing. 88, 3, p. 391-399 9 p.

    Research output: Contribution to journalArticle

  13. A 2.2ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration

    Lu, P., Wu, Y. & Piero Andreani, 2016 Mar 29, In : IEEE Transactions on Circuits and Systems - II - Express Briefs. p. 1019 - 1023 5 p.

    Research output: Contribution to journalArticle

  14. 2015
  15. A 0.6-3.0 GHz 65 nm CMOS Radio Receiver with DS-based A/D-Converting Channel-Select Filters

    Nejdel, A., Xiaodong Liu, Palm, M., Sundström, L., Markus Törmänen, Henrik Sjöland & Pietro Andreani, 2015, [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., 4 p.

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  16. A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process

    Fanori, L., Mahmoud, A., Mattsson, T., Caputa, P., Rämö, S. & Piero Andreani, 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE - Institute of Electrical and Electronics Engineers Inc., p. 195 - 198

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  17. A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

    Mahmoud, A., Piero Andreani & Lu, P., 2015, Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC).

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  18. A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer

    Radjen, D., Anderson, M., Sundstrom, L. & Pietro Andreani, 2015, In : Analog Integrated Circuits and Signal Processing. 84, 3, p. 409-420

    Research output: Contribution to journalArticle

  19. Digital background calibration in continuous-time delta-sigma analog to digital converters

    Siyu Tan, Miao, Y., Andersson, M., Joachim Rodrigues & Piero Andreani, 2015, Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015 . IEEE - Institute of Electrical and Electronics Engineers Inc.

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  20. 2014
  21. A 1-1 MASH 2-D Vernier Time-to-Digital Converter with 2nd-order noise shaping

    Lu, P. & Pietro Andreani, 2014, [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., p. 1324-1327 4 p.

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  22. A 2.4-to-5.3GHz Dual-Core CMOS VCO with Concentric 8-Shaped Coils

    Fanori, L., Mattsson, T. & Pietro Andreani, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). IEEE - Institute of Electrical and Electronics Engineers Inc., Vol. 57. p. 370

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  23. A Class-D CMOS DCO with an on-chip LDO

    Fanori, L., Mattsson, T. & Pietro Andreani, 2014, Proceedings Of The 40th European Solid-State Circuit Conference (ESSCIRC 2014). IEEE - Institute of Electrical and Electronics Engineers Inc., p. 335-338

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  24. A Filtering Delta Sigma ADC for LTE and Beyond

    Andersson, M., Andersson, M., Sundström, L., Mattisson, S. & Pietro Andreani, 2014, In : IEEE Journal of Solid-State Circuits. 49, 7, p. 1535-1547

    Research output: Contribution to journalArticle

  25. A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier

    Radjen, D., Anderson, M., Sundstrom, L. & Pietro Andreani, 2014, In : Analog Integrated Circuits and Signal Processing. 80, 3, p. 387-397

    Research output: Contribution to journalArticle

  26. An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS

    Xiaodong Liu, Andersson, M., Anderson, M., Sundstrom, L. & Pietro Andreani, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., p. 2337-2340

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  27. A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers

    Liscidini, A., Fanori, L., Pietro Andreani & Castello, R., 2014, In : IEEE Journal of Solid-State Circuits. 49, 3, p. 646-656

    Research output: Contribution to journalArticle

  28. 2013
  29. A 2.7-6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2

    Bevilacqua, A. & Pietro Andreani, 2013, In : Analog Integrated Circuits and Signal Processing. 74, 1, p. 11-20

    Research output: Contribution to journalArticle

  30. A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

    Lu, P., Pietro Andreani & Liscidini, A., 2013, In : Analog Integrated Circuits and Signal Processing. 76, 2, p. 195-206

    Research output: Contribution to journalArticle

  31. A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency

    Lu, P., Pietro Andreani & Liscidini, A., 2013, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013. IEEE - Institute of Electrical and Electronics Engineers Inc., p. 151-154

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  32. A 9MHz Filtering ADC with Additional 2nd-Order Delta-Sigma Modulator Noise Suppression

    Andersson, M., Andersson, M., Sundström, L. & Pietro Andreani, 2013, Proceedings of the ESSCIRC (ESSCIRC), 2013. IEEE - Institute of Electrical and Electronics Engineers Inc., p. 323-326

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  33. A Push-Pull Class-C CMOS VCO

    Mazzanti, A. & Pietro Andreani, 2013, In : IEEE Journal of Solid-State Circuits. 48, 3, p. 724-732

    Research output: Contribution to journalArticle

  34. A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing

    Ye, D., Lu, P., Pietro Andreani & Zee, R. V. D., 2013, [Host publication title missing]. ISCAS, p. 169-172

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  35. Class-D CMOS Oscillators

    Fanori, L. & Pietro Andreani, 2013, In : IEEE Journal of Solid-State Circuits. 48, 12, p. 3105-3119

    Research output: Contribution to journalArticle

  36. Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs

    Fanori, L. & Pietro Andreani, 2013, In : IEEE Journal of Solid-State Circuits. 48, 7, p. 1730-1740

    Research output: Contribution to journalArticle

  37. Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations

    Andersson, M., Sundström, L., Andersson, M. & Pietro Andreani, 2013, In : Analog Integrated Circuits and Signal Processing. 76, 3, p. 353-366

    Research output: Contribution to journalArticle

  38. 2012
  39. A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS

    Abdulaziz, M., Shakir, M., Lu, P. & Pietro Andreani, 2012.

    Research output: Contribution to conferenceAbstract

  40. A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps

    Lu, P., Liscidini, A. & Pietro Andreani, 2012, In : IEEE Journal of Solid-State Circuits. 47, 7, p. 1626-1635

    Research output: Contribution to journalArticle

  41. A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations

    Andersson, M., Andersson, M., Sundström, L. & Pietro Andreani, 2012, IEEE Asian Solid State Circuits Conference (A-SSCC), 2012. IEEE - Institute of Electrical and Electronics Engineers Inc., p. 245-248

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  42. A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter

    Lu, P., Wu, Y. & Pietro Andreani, 2012, [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., p. 2593-2596 4 p.

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  43. A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter

    Lu, P., Liscidini, A. & Pietro Andreani, 2012, (Accepted/In press). 4 p.

    Research output: Contribution to conferencePaper, not in proceeding

  44. A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback

    Radjen, D., Andersson, M., Sundström, L. & Pietro Andreani, 2012, In : Analog Integrated Circuits and Signal Processing.

    Research output: Contribution to journalArticle

  45. Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture

    Sundström, L., Andersson, M., Andersson, M. & Pietro Andreani, 2012, Radio Frequency Integrated Circuits Symposium (RFIC), 2012. IEEE - Institute of Electrical and Electronics Engineers Inc., p. 265-268

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  46. Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference

    Corsi, M., Pietro Andreani, Ki, W-H., Chien, G. & Kenney, J., 2012, In : IEEE Journal of Solid-State Circuits. 47, 12, p. 2859-2864

    Research output: Contribution to journalDebate/Note/Editorial

  47. 2011
  48. A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS

    Abdulaziz, M., Shakir, M., Lu, P. & Pietro Andreani, 2011, [Host publication title missing]. 4 p.

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  49. A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution

    Lu, P., Pietro Andreani & Liscidini, A., 2011, [Host publication title missing]. p. 459-462

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  50. A 9-band WCDMA/EDGE transceiver supporting HSPA evolution

    Nilsson, M., Mattisson, S., Klemmer, N., Andersson, M., Arnborg, T., Caputa, P., Ek, S., Fan, L., Fredriksson, H., Garrigues, F., Geis, H., Hagberg, H., Hedestig, J., Huang, H., Kagan, Y., Karlsson, N., Kinzel, H., Mattsson, T., Mills, T., Mu, F. & 21 others, Mårtensson, A., Nicklasson, L., Oredsson, F., Ozdemir, U., Park, F., Pettersson, T., Påhlsson, T., Pålsson, M., Ramon, S., Sandgren, M., Sandrup, P., Stenman, A-K., Strandberg, R., Sundström, L., Tillman, F., Tired, T., Uppathil, S., Walukas, J., Westesson, E., Zhang, X. & Pietro Andreani, 2011, [Host publication title missing]. p. 366-368

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  51. A continuous time delta sigma modulator with reduced clock jitter through DSCR feedback

    Radjen, D., Andersson, M., Sundström, L. & Pietro Andreani, 2011.

    Research output: Contribution to conferencePaper, not in proceeding

  52. A Digital PLL with a Multi-Delay Coarse-Fine TDC

    Wu, Y., Lu, P. & Pietro Andreani, 2011, [Host publication title missing]. 4 p.

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  53. A mixed mode design flow for multi GHz ADPLLs

    Shakir, M., Abdulaziz, M., Lu, P. & Pietro Andreani, 2011, [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., 4 p.

    Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

  54. A TX VCO for WCDMA/EDGE in 90 nm RF CMOS

    Pietro Andreani, Kozmin, K., Sandrup, P., Nilsson, M. & Mattsson, T., 2011, In : IEEE Journal of Solid-State Circuits. 46, 7, p. 1618-1626

    Research output: Contribution to journalArticle

Previous 1 2 3 Next