1/f Noise Sources in Dual-Gated Indium Arsenide Nanowire Transistors

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Abstract

1/f noise is studied in dual-gated InAs nanowire transistors consisting of an omega top gate with high-k atomic layer deposited dielectric and silicon dioxide to substrate back gate. Noise spectra at varying gate bias combinations are compared from devices with differing top-gate lengths to separate the noise contributions of the top-gated channel from the ungated access portion, including the metal-nanowire contacts. For a given device geometry, it is possible to bias the device into four different regimes where the resistance and the noise amplitude can each be independently dominated by either the channel or the access/contact regions. When the device is fully in the on state, the access/contact regions dominate both resistance and noise. When the device is operating near or below threshold, the channel dominates resistance and noise. For the lowest amount of overall 1/f noise, most of the nanowire should be covered by the top gate, minimizing the access region length.

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Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Condensed Matter Physics

Keywords

  • Indium Arsenide, low-frequency noise, nanowire FETs
Original languageEnglish
Pages (from-to)1980-1987
JournalIEEE Transactions on Electron Devices
Volume59
Issue number7
Publication statusPublished - 2012
Publication categoryResearch
Peer-reviewedYes