A 0.13µm CMOS ΔΣ PLL FM Transmitter

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.

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Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publication[Host publication title missing]
Number of pages4
Publication statusPublished - 2011
Publication categoryResearch
Peer-reviewedYes
Event29th Norchip conference, 2011 - Lund, Lund, Sweden
Duration: 2011 Nov 142011 Nov 15

Conference

Conference29th Norchip conference, 2011
CountrySweden
CityLund
Period2011/11/142011/11/15