A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Sepctre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm<sup>2</sup>. © 2007 IEEE.

Details

Authors
  • Cheng Chen
  • Jiren Yuan
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Preprocessing blocks, Auto-zero calibration, Wide input bandwidth, Sepctre simulation
Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages1709-1712
Publication statusPublished - 2007
Publication categoryResearch
Peer-reviewedYes
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 2007 May 272007 May 30

Publication series

Name
ISSN (Print)2158-1525
ISSN (Electronic)0271-4310

Conference

Conference2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
CountryUnited States
CityNew Orleans, LA
Period2007/05/272007/05/30