A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding


Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.


Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publication2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)
PublisherIEEE--Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)978-1-4799-2452-3
Publication statusPublished - 2013
Publication categoryResearch
Event2013 IEEE International Conference on Electronics, Circuits, and Systems - Abu Dhabi, U ARAB EMIRATES
Duration: 2013 Dec 82013 Dec 11


Conference2013 IEEE International Conference on Electronics, Circuits, and Systems