This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5 mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.
|Title of host publication||ESSCIRC 2007: Proceedings of the33rd EuropeanSolid State Circuits Conference|
|Publisher||IEEE - Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2007|
|Event||33rd European Solid-State Circuits Conference - Munich, Germany|
Duration: 2007 Sep 11 → 2007 Sep 13
|Conference||33rd European Solid-State Circuits Conference|
|Period||2007/09/11 → 2007/09/13|