A 312-MHz CT Delta Sigma modulator using a SC feedback DAC with reduced peak current

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5 mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.

Details

Authors
  • Martin Anderson
  • Lars Sundström
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publicationESSCIRC 2007: Proceedings of the33rd EuropeanSolid State Circuits Conference
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages240-243
ISBN (Print)978-1-4244-1125-2
Publication statusPublished - 2007
Publication categoryResearch
Peer-reviewedYes
Event33rd European Solid-State Circuits Conference - Munich, Germany
Duration: 2007 Sep 112007 Sep 13

Publication series

Name
ISSN (Print)1930-8833

Conference

Conference33rd European Solid-State Circuits Conference
CountryGermany
CityMunich
Period2007/09/112007/09/13