A 350 uW Sign-Bit Architecture for Multi-parameter Estimation During OFDM Acquisition in 65nm CMOS

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding


Correct estimation of symbol timing, Carrier Frequency
Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial
in Orthogonal Frequency Division Multiplexing (OFDM) communication.
Typically, high estimation accuracy is desired, but often
comes with increased complexity. Which has a direct repercussion
in energy consumption. In this article, an architecture based on
Sign-Bit estimation with low complexity, and hence low power
dissipation, is presented. The architecture, is capable of estimating
the afore-mentioned parameters in virtually any OFDM
standard. The proof of concept has been fabricated in 65 nm
CMOS technology with low-power high-VT cells. Measurements
performed with supply voltage of 1.2V. resulted in a power
dissipation of 350 μW, 6 times smaller to that of an equivalent
8-bit architecture, and the lowest power density reported in


Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Publication statusAccepted/In press - 2015
Publication categoryResearch
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2015 - Lisbon, Portugal
Duration: 2015 May 242015 May 27


ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2015