A 70 pJ/b configurable 64-QAM soft MIMO detector

Research output: Contribution to journalArticle


An area and power efficient high-throughput VLSI implementation of a 4 × 4, 64-QAM soft multiple-input-multiple-output (MIMO) detector, that is suitable for high-order constellation schemes is presented. The proposed MIMO detector utilizes information contained in the discarded paths to improve the bit-error-rate (BER) performance, and then reduces computational complexity using three innovative improvement ideas. The proposed design is fabricated and fully tested in a 130 nm CMOS technology. Operating with a 270 MHz clock, the design achieves up to 655 Mbps throughput with 195 mW power dissipation at 1.32 V supply. Synthesis results in 65 nm CMOS technology shows that the proposed soft-output MIMO detector attains a peak coded data throughput of 2 Gbps. Furthermore, this detector is also suitable for low-power mobile applications that require high data rates, achieving a low decoding energy per bit of 70.3 pJ/bit at 1.1 V supply, while providing a data throughput of 640 Mbps in a 65 nm CMOS technology. The proposed design has the best throughput per unit area among all reported fabricated designs to-date


External organisations
  • Sharif University of Technology
  • University of Toronto
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Other Electrical Engineering, Electronic Engineering, Information Engineering


  • Application-specific integrated circuit (ASIC) implementation, K-Best detectors, Multiple-input-multiple-output (MIMO) detection, Soft MIMO detectors
Original languageEnglish
Pages (from-to)74-86
Number of pages13
JournalIntegration, the VLSI Journal
Publication statusPublished - 2018 May 24
Publication categoryResearch