A digitally controlled shunt capacitor CMOS delay line
Research output: Contribution to journal › Article
Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 x 0.5 ns delay under large temperature, supply voltage, and technological process quality variations.
|Research areas and keywords||
Subject classification (UKÄ) – MANDATORY
|Journal||Analog Integrated Circuits and Signal Processing|
|Publication status||Published - 1999|
The information about affiliations in this record was updated in December 2015. The record was previously connected to the following departments: Department of Electroscience (011041000)