A GSM speech coder implemented on a customized processor architecture

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

- A GSM speech coder has been implemented
on a custom DSP using a system for design
of arbitrary processor architectures. The speech
coder has been generated from a high level description
to netlist. The design system allows implementation
in various technologies and a netlist
for Plessey gate array has been generated. Due
to the rigid specification of the speech coder, the
advantages of a custom DSP can not be fully utilized
and a result in clock cycles and ROM storage
comparable to a standard DSP is achieved.

Details

Authors
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publicationISCAS '93, 1993 IEEE International Symposium on Circuits and Systems
Pages235-238
Publication statusPublished - 1993
Publication categoryResearch
Peer-reviewedYes
EventIEEE International Symposium on Circuits and Systems (ISCAS), 1993 - Chicago, United States
Duration: 1993 May 31993 May 6

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 1993
CountryUnited States
CityChicago
Period1993/05/031993/05/06