A hardware efficiency analysis for simplified trellis decoding blocks

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.

Details

Authors
Organisations
Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Trellis decoding blocks, Computational operations, Hardware efficiency
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Pages128-132
Volume2005
ISBN (Print)0-7803-9333-3
Publication statusPublished - 2005
Publication categoryResearch
Peer-reviewedYes
EventIEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS) - Athens, Greece
Duration: 2005 Nov 22005 Nov 4

Publication series

Name
Volume2005
ISSN (Print)1520-6130

Conference

ConferenceIEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS)
CountryGreece
CityAthens
Period2005/11/022005/11/04