Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.
|Title of host publication||[Host publication title missing]|
|Publisher||IEEE - Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2005|
|Event||IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS) - Athens, Greece|
Duration: 2005 Nov 2 → 2005 Nov 4
|Conference||IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS)|
|Period||2005/11/02 → 2005/11/04|