Abstract
Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.
Details
| Authors |
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| Organisations |
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| Research areas and keywords |
- Electrical Engineering, Electronic Engineering, Information Engineering
- Trellis decoding blocks, Computational operations, Hardware efficiency
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| Original language | English |
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| Title of host publication | [Host publication title missing] |
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| Publisher | IEEE - Institute of Electrical and Electronics Engineers Inc. |
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| Pages | 128-132 |
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| Volume | 2005 |
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| ISBN (Print) | 0-7803-9333-3 |
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| Publication status | Published - 2005 |
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| Publication category | Research |
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| Peer-reviewed | Yes |
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| Event | IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS) - Athens, Greece
Duration: 2005 Nov 2 → 2005 Nov 4 |
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| Name | |
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| Volume | 2005 |
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| ISSN (Print) | 1520-6130 |
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| Conference | IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS) |
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| Country | Greece |
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| City | Athens |
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| Period | 2005/11/02 → 2005/11/04 |
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