A Highly Parallelized MIMO Detector for Vector-Based Reconfigurable Architectures

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding


This paper presents a highly parallelized MIMO signal detection algorithm targeting vector-based reconfigurable architectures. The detector achieves high data-level parallelism and near-ML performance by adopting a vector-architecture-friendly technique - parallel node perturbation. To further reduce the computational complexity, imbalanced node and successive partial node expansion schemes in conjunction with sorted QR decomposition are applied. The effectiveness of the proposed algorithm is evaluated by simulations performed on a simplified 4x4 MIMO LTE-A testbed and operation analysis. Compared to the K-Best detector and fixed-complexity sphere decoder (FSD), the number of visited nodes in the proposed algorithm is reduced by 15 and 1.9 times respectively, with less than 1dB performance degradation. Benefiting from the fully deterministic non-iterative dataflow structure, reconfiguration rate is 95% less than that of the K-Best detector and 17% less than the case of FSD.


Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering


  • MIMO, signal detection, vector processor, data parallelization
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages6
Publication statusPublished - 2013
Publication categoryResearch
EventIEEE Wireless Communications and Networking Conference (WCNC), 2013 - Shanghai, China
Duration: 2013 Apr 72013 Apr 10


ConferenceIEEE Wireless Communications and Networking Conference (WCNC), 2013

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