A High-Speed QR Decomposition Processor for Carrier-Aggregated LTE-A Downlink Systems

Research output: Contribution to conferencePaper, not in proceeding

Abstract

This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77mm2 and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 219mW.

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Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Number of pages4
Publication statusPublished - 2013
Publication categoryResearch
Peer-reviewedYes
EventEuropean Conference on Circuit Theory and Design (ECCTD 2013) - Dresden, Germany
Duration: 2013 Sep 82013 Sep 12

Conference

ConferenceEuropean Conference on Circuit Theory and Design (ECCTD 2013)
CountryGermany
CityDresden
Period2013/09/082013/09/12

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