A low latency and area efficient FFT processor for massive MIMO systems

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding


A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.


Research areas and keywords

Subject classification (UKÄ) – MANDATORY

  • Other Electrical Engineering, Electronic Engineering, Information Engineering
  • Communication Systems


  • FFT, Massive MIMO, VLSI implementation, ASIC implementation, FPGA implementation, low latency, IFFT
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings
PublisherIEEE - Institute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)978-1-4673-6853-7
ISBN (Print)978-1-5090-1427-9
Publication statusPublished - 2017 Sep 28
Publication categoryResearch
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: 2017 May 282017 May 31


Conference50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States