A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands

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Abstract

A considerable part of latency in the baseband of massive multiple-input multiple-output (MIMO) systems is introduced by orthogonal frequency division multiplexing (OFDM) (de)modulation. To address the low-latency demand of massive MIMO systems, a fast Fourier transform (FFT) processor and corresponding reordering scheme are proposed, which reduce the processing latency and reordering latency of OFDM-based systems, respectively. The main idea is to utilize the OFDM guard bands to decrease the number of required computations and thus the processing time. In case of a 2048-point IFFT, the proposed scheme leads to 42% reduction in latency compared to the reported pipelined schemes at the cost of 4% additional memory, which is around 2.4% of the total chip area. To realize this idea, a modified pipelined architecture with a reorganized memory structure and also an efficient data scheduling mechanism for memories and butterflies are developed. Using the proposed scheme, a 2048-point FFT/IFFT processor has been implemented in a 28 nm complementary metal-oxide-semiconductor technology. The post-layout simulations show that our design achieves a throughput of 0.6 GS/s and 1200 clock cycles latency, the lowest latency reported to-date for single-input pipelined FFT/IFFT architectures.

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Subject classification (UKÄ) – MANDATORY

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • FFT processor, massive MIMO, low latency, pipelined architecture, ASIC implementation, OFDM, guard band, VLSI architecture, hardware implementation
Original languageEnglish
Pages (from-to)1-12
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Publication statusPublished - 2019 Feb 27
Publication categoryResearch
Peer-reviewedYes