A low noise PLL based FM audio transmitter in 0.35 μm CMOS technology

Research output: Chapter in Book/Report/Conference proceedingPaper in conference proceeding

Abstract

PLL (Phase Locked Loop) based frequency synthesizers are widely used in the wireless communication field. This paper puts focus on the design and implementation of a 60dB SNR (Signal to Noise Ratio) FM transmitter, which realizes direct frequency modulation of audio signal by utilizing a carrier frequency ranging from 78MHz to 108MHz, with a 100 kHz channel selection resolution. Fabricated in standard 0.35μm CMOS technology, this PLL's core circuit takes an area of 745×700 μm2. The transmitter has a total power consumption of below 56mW for a 3V supply, and the strongest measured spur is below -50dBc.

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Subject classification (UKÄ) – MANDATORY

  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Title of host publication[Host publication title missing]
PublisherIEEE--Institute of Electrical and Electronics Engineers Inc.
Pages202-205
Number of pages4
ISBN (Print)978-1-4244-6735-8
Publication statusPublished - 2010
Publication categoryResearch
Peer-reviewedYes
EventPacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010 Asia - Shanghai
Duration: 2010 Sep 22 → …

Conference

ConferencePacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010 Asia
Period2010/09/22 → …