A New Digital Front-End for Flexible Reception in Software Defined Radio

Research output: Contribution to journalArticle

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A New Digital Front-End for Flexible Reception in Software Defined Radio. / Diaz, Isael; Zhang, Chenxin; Hollevoet, Lieven; Svensson, Jim; Rodrigues, Joachim; Wilhelmsson, Leif; Olsson, Thomas; Van der Perre, Liesbet; Öwall, Viktor.

In: Microprocessors and Microsystems, Vol. 39, No. 8, 2015, p. 889-900.

Research output: Contribution to journalArticle

Harvard

Diaz, I, Zhang, C, Hollevoet, L, Svensson, J, Rodrigues, J, Wilhelmsson, L, Olsson, T, Van der Perre, L & Öwall, V 2015, 'A New Digital Front-End for Flexible Reception in Software Defined Radio', Microprocessors and Microsystems, vol. 39, no. 8, pp. 889-900. https://doi.org/10.1016/j.micpro.2015.03.001

APA

Diaz, I., Zhang, C., Hollevoet, L., Svensson, J., Rodrigues, J., Wilhelmsson, L., Olsson, T., Van der Perre, L., & Öwall, V. (2015). A New Digital Front-End for Flexible Reception in Software Defined Radio. Microprocessors and Microsystems, 39(8), 889-900. https://doi.org/10.1016/j.micpro.2015.03.001

CBE

MLA

Vancouver

Author

Diaz, Isael ; Zhang, Chenxin ; Hollevoet, Lieven ; Svensson, Jim ; Rodrigues, Joachim ; Wilhelmsson, Leif ; Olsson, Thomas ; Van der Perre, Liesbet ; Öwall, Viktor. / A New Digital Front-End for Flexible Reception in Software Defined Radio. In: Microprocessors and Microsystems. 2015 ; Vol. 39, No. 8. pp. 889-900.

RIS

TY - JOUR

T1 - A New Digital Front-End for Flexible Reception in Software Defined Radio

AU - Diaz, Isael

AU - Zhang, Chenxin

AU - Hollevoet, Lieven

AU - Svensson, Jim

AU - Rodrigues, Joachim

AU - Wilhelmsson, Leif

AU - Olsson, Thomas

AU - Van der Perre, Liesbet

AU - Öwall, Viktor

PY - 2015

Y1 - 2015

N2 - Future mobile terminals are expected to support an ever increasing number of Radio Access Technologies (RAT) concurrently. This imposes a challenge to terminal designers already today. Software Defined Radio (SDR) solutions are a compelling alternative to address this issue in the digital baseband, given its high flexibility and low Non-Recurring Engineering (NRE) cost. However, the challenge still remains in the Digital Front-End (DFE), where many operations are too complex or energy hungry to be implemented as software instructions. Thus, new architectures are needed to feed the SDR digital baseband while keeping complexity and energy consumption at bay. In this article the architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals is presented. The flexibility needed for multi-standard support is demonstrated by detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. Moreover, the proposed architecture has been fabricated in a 65 nm CMOS low power high-VT cell technology in a die size of 5 mm2. The core module of the DFE-Rx, the synchronization engine, has been measured at 1.2 V and reports an average power consumption of 1.9 mW during Wireless Local Area Network (WLAN) reception and 1.6 mW during configuration, while running at 10 MHz.

AB - Future mobile terminals are expected to support an ever increasing number of Radio Access Technologies (RAT) concurrently. This imposes a challenge to terminal designers already today. Software Defined Radio (SDR) solutions are a compelling alternative to address this issue in the digital baseband, given its high flexibility and low Non-Recurring Engineering (NRE) cost. However, the challenge still remains in the Digital Front-End (DFE), where many operations are too complex or energy hungry to be implemented as software instructions. Thus, new architectures are needed to feed the SDR digital baseband while keeping complexity and energy consumption at bay. In this article the architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals is presented. The flexibility needed for multi-standard support is demonstrated by detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. Moreover, the proposed architecture has been fabricated in a 65 nm CMOS low power high-VT cell technology in a die size of 5 mm2. The core module of the DFE-Rx, the synchronization engine, has been measured at 1.2 V and reports an average power consumption of 1.9 mW during Wireless Local Area Network (WLAN) reception and 1.6 mW during configuration, while running at 10 MHz.

U2 - 10.1016/j.micpro.2015.03.001

DO - 10.1016/j.micpro.2015.03.001

M3 - Article

VL - 39

SP - 889

EP - 900

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

IS - 8

ER -