A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS

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Abstract

A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and the design of integrated phased array transceivers becomes more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 × 700 μm2. Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of −110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.

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  • Electrical Engineering, Electronic Engineering, Information Engineering
Original languageEnglish
Pages (from-to)309-318
JournalAnalog Integrated Circuits and Signal Processing
Volume67
Issue number3
Publication statusPublished - 2011
Publication categoryResearch
Peer-reviewedYes