A Self-aligned Gate-last Process applied to All-III-V CMOS on Si

Research output: Contribution to journalArticle

Bibtex

@article{357118b824394b22b9bbeb861579c189,
title = "A Self-aligned Gate-last Process applied to All-III-V CMOS on Si",
abstract = "Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are co-processed and co-integrated using a gate-last process, enabling short gate-lengths (Lg=40 nm) and allowing selective digital etching of the channel. Two different common gate-stacks, including various pre-treatments, were compared and evaluated. The process was optimized to achieve high n-type performance while demonstrating p-type operation. The best n-type device is scaled down to 12 nm diameter and has a peak transconductance of 2.6 mS/μm combined with a low Ron of 317 Ω·μm while the p-type exhibit 74 μS/μm. In spite of increased complexity due to co-integration, our n-type InAs transistors demonstrate increased drive-current, 1.8 mA/μm, compared to earlier publications.",
keywords = "CMOS, GaSb, III-V, InAs, MOSFET, nanowire, Vertical",
author = "Adam Jonsson and Johannes Svensson and Wernersson, {Lars Erik}",
year = "2018",
month = jul,
doi = "10.1109/LED.2018.2837676",
language = "English",
volume = "39",
pages = "935--938",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",
number = "7",

}