A Self-aligned Gate-last Process applied to All-III-V CMOS on Si

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T1 - A Self-aligned Gate-last Process applied to All-III-V CMOS on Si

AU - Jonsson, Adam

AU - Svensson, Johannes

AU - Wernersson, Lars Erik

PY - 2018/7

Y1 - 2018/7

N2 - Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are co-processed and co-integrated using a gate-last process, enabling short gate-lengths (Lg=40 nm) and allowing selective digital etching of the channel. Two different common gate-stacks, including various pre-treatments, were compared and evaluated. The process was optimized to achieve high n-type performance while demonstrating p-type operation. The best n-type device is scaled down to 12 nm diameter and has a peak transconductance of 2.6 mS/μm combined with a low Ron of 317 Ω·μm while the p-type exhibit 74 μS/μm. In spite of increased complexity due to co-integration, our n-type InAs transistors demonstrate increased drive-current, 1.8 mA/μm, compared to earlier publications.

AB - Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are co-processed and co-integrated using a gate-last process, enabling short gate-lengths (Lg=40 nm) and allowing selective digital etching of the channel. Two different common gate-stacks, including various pre-treatments, were compared and evaluated. The process was optimized to achieve high n-type performance while demonstrating p-type operation. The best n-type device is scaled down to 12 nm diameter and has a peak transconductance of 2.6 mS/μm combined with a low Ron of 317 Ω·μm while the p-type exhibit 74 μS/μm. In spite of increased complexity due to co-integration, our n-type InAs transistors demonstrate increased drive-current, 1.8 mA/μm, compared to earlier publications.

KW - CMOS

KW - GaSb

KW - III-V

KW - InAs

KW - MOSFET

KW - nanowire

KW - Vertical

UR - http://www.scopus.com/inward/record.url?scp=85047019807&partnerID=8YFLogxK

U2 - 10.1109/LED.2018.2837676

DO - 10.1109/LED.2018.2837676

M3 - Article

AN - SCOPUS:85047019807

VL - 39

SP - 935

EP - 938

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 7

ER -