An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment

TY - JOUR

T1 - An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment

AU - Larsson, Erik

PY - 2008

Y1 - 2008

N2 - The semiconductor technology development makes it possible to fabricate increasingly advanced integrated circuits (ICs). However, because of imperfections at manufacturing, each individual IC must be tested. A major problem at IC manufacturing test is the increasing test data volume as it leads to high automatic test equipment (ATE) memory requirement, long test application time and low throughput. In contrast with existing approaches, which address either test data compression for ATE memory reduction or abort-on-fail testing for test time minimisation, an architecture that supports both test data compression and abort-on-fail testing at clock-cycle granularity is proposed, and hence both ATE memory reduction and test application time minimisation are addressed. Further, the proposed architecture efficiently tackles low throughput as the architecture allows multi-site testing at a constant ATE memory requirement, which is independent of the number of tested ICs. Advantages of the architecture, compared with test compression architecture, are that diagnostic capabilities are not reduced and there is no need for special handling of unknowns (X) in the produced test responses (PR). Experiments on ISCAS benchmark circuits and an industrial circuit have been performed.

AB - The semiconductor technology development makes it possible to fabricate increasingly advanced integrated circuits (ICs). However, because of imperfections at manufacturing, each individual IC must be tested. A major problem at IC manufacturing test is the increasing test data volume as it leads to high automatic test equipment (ATE) memory requirement, long test application time and low throughput. In contrast with existing approaches, which address either test data compression for ATE memory reduction or abort-on-fail testing for test time minimisation, an architecture that supports both test data compression and abort-on-fail testing at clock-cycle granularity is proposed, and hence both ATE memory reduction and test application time minimisation are addressed. Further, the proposed architecture efficiently tackles low throughput as the architecture allows multi-site testing at a constant ATE memory requirement, which is independent of the number of tested ICs. Advantages of the architecture, compared with test compression architecture, are that diagnostic capabilities are not reduced and there is no need for special handling of unknowns (X) in the produced test responses (PR). Experiments on ISCAS benchmark circuits and an industrial circuit have been performed.

KW - integrated circuits

KW - testing

KW - test data volume

KW - compression

KW - abort-on-fail

U2 - 10.1049/iet-cdt:20070078

DO - 10.1049/iet-cdt:20070078

M3 - Article

VL - 2

SP - 275

EP - 284

JO - IET Computers and Digital Techniques

JF - IET Computers and Digital Techniques

SN - 1751-8601

IS - 4

ER -